MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Scalable and reliable communication for hardware transactional memory
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Vicis: a reliable network for unreliable silicon
Proceedings of the 46th Annual Design Automation Conference
Fault-tolerant cache coherence protocols for CMPs: evaluation and trade-offs
HiPC'08 Proceedings of the 15th international conference on High performance computing
Low-overhead error detection for networks-on-chip
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
International Journal of High Performance Systems Architecture
Fault-Tolerant Flow Control in On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complement routing: A methodology to design reliable routing algorithm for Network on Chips
Microprocessors & Microsystems
Optimizing power and performance for reliable on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing
Journal of Parallel and Distributed Computing
A distributed and topology-agnostic approach for on-line NoC testing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
Low-cost fault-tolerant switch allocator for network-on-chip routers
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Formally enhanced runtime verification to ensure NoC functional correctness
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Benefits of selective packet discard in networks-on-chip
ACM Transactions on Architecture and Code Optimization (TACO)
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Computers and Electrical Engineering
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Fault Tolerant Hierarchical Network on Chip Router Architecture
Journal of Electronic Testing: Theory and Applications
Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs
Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology
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The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are rapidly becoming a force to be reckoned with. This spiraling trend highlights the importance of detailed analysis of these reliability hazards and the incorporation of comprehensive protection measures into all Network-on-Chip (NoC) designs. In this paper, we examine the impact of transient failures on the reliability of on-chip interconnects and develop comprehensive counter-measures to either prevent or recover from them. In this regard, we propose several novel schemes to remedy various kinds of soft error symptoms, while keeping area and power overhead at a minimum. Our proposed solutions are architected to fully exploit the available infrastructures in an NoC and enable versatile reuse of valuable resources. The effectiveness of the proposed techniques has been validated using a cycle-accurate simulator.