Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip
ITNG '07 Proceedings of the International Conference on Information Technology
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
Reliability in Application Specific Mesh-Based NoC Architectures
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Design of Optimal Architectures Using Homogeneous Routers for Application Specific Network on Chip
ICETET '08 Proceedings of the 2008 First International Conference on Emerging Trends in Engineering and Technology
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
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As the integration of transistors on today's embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the salient problem, since regarding to the inaccessible failures of on-chip elements, there must be some levels of embedded fault tolerance techniques. In this paper, an innovated technique is revealed providing fault tolerance in the on-chip networks over single and multiple permanent switch failures. The experimental results achieved by the system simulation in SystemC TLM environment are validated with the mathematical analysis modeled for system reliability that we extend in this paper, which demonstrate the extensive reliability enhancement of this paradigm. Along with the system improvement, silicon area overhead is calculated utilizing VHDL low level simulation and Orion synthesis.