Route packets, not wires: on-chip inteconnection networks

Authors:
William J. Dally;Brian Towles
Affiliations:
Computer Systems Laboratory, Stanford University, Stanford, CA;Computer Systems Laboratory, Stanford University, Stanford, CA
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

Citing 4
Cited 646

Let's route packets instead of wires

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Trends toward on-chip networked microsystems

International Journal of High Performance Computing and Networking
A new selection policy for adaptive routing in network on chip

EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Mesh-of-tree deterministic routing for network-on-chip architecture

Proceedings of the 18th ACM Great Lakes symposium on VLSI
MLMIN: A multicore processor and parallel computer network topology for multicast

Computers and Operations Research
Designing efficient irregular networks for heterogeneous systems-on-chip

Journal of Systems Architecture: the EUROMICRO Journal
A monitoring-aware network-on-chip design flow

Journal of Systems Architecture: the EUROMICRO Journal
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip

Journal of Systems Architecture: the EUROMICRO Journal
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

Journal of Systems Architecture: the EUROMICRO Journal
Invited paper: Network-on-Chip design and synthesis outlook

Integration, the VLSI Journal
Software-directed combined cpu/link voltage scaling fornoc-based cmps

SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
A domain specific interconnect for reconfigurable computing

Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems
QoS-supported on-chip communication for multi-processors

International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Run-time integration of reconfigurable video processing systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A consistency architecture for hierarchical shared caches

Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Reduction of a polling network to a single node

Queueing Systems: Theory and Applications
Variation-adaptive feedback control for networks-on-chip with multiple clock domains

Proceedings of the 45th annual Design Automation Conference
Application mapping for chip multiprocessors

Proceedings of the 45th annual Design Automation Conference
ADAM: run-time agent-based distributed application mapping for on-chip communication

Proceedings of the 45th annual Design Automation Conference
On reliable modular testing with vulnerable test access mechanisms

Proceedings of the 45th annual Design Automation Conference
PowerAntz: distributed power sharing strategy for network on chip

Proceedings of the 13th international symposium on Low power electronics and design
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A Network of Time-Division Multiplexed Wiring for FPGAs

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Statistical Approach to NoC Design

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Reducing the Interconnection Network Cost of Chip Multiprocessors

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
In-band cross-trigger event transmission for transaction-based debug

Proceedings of the conference on Design, automation and test in Europe
Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor

Proceedings of the conference on Design, automation and test in Europe
Re-examining the use of network-on-chip as test access mechanism

Proceedings of the conference on Design, automation and test in Europe
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology

Proceedings of the conference on Design, automation and test in Europe
Comparison of memory write policies for NoC based multicore cache coherent systems

Proceedings of the conference on Design, automation and test in Europe
Minimizing virtual channel buffer for routers in on-chip communication architectures

Proceedings of the conference on Design, automation and test in Europe
Multicast parallel pipeline router architecture for network-on-chip

Proceedings of the conference on Design, automation and test in Europe
BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs

Proceedings of the conference on Design, automation and test in Europe
Developing mesochronous synchronizers to enable 3D NoCs

Proceedings of the conference on Design, automation and test in Europe
Design and performance evaluation of combined first-fit task allocation and migration strategies in mesh multiprocessor systems

Parallel Computing
A Link-Load Balanced Low Energy Mapping and Routing for NoC

ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications

ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures

ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
Reducing Packet Dropping in a Bufferless NoC

Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
A Communication-Aware Topological Mapping Technique for NoCs

Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
A Hardware-Software Design Framework for Distributed Cellular Computing

ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Efficiency and scalability of barrier synchronization on NoC based many-core architectures

CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Asynchronous transient resilient links for NoC

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Distributed flit-buffer flow control for networks-on-chip

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A new modelling approach of wormhole-switched networks with finite buffers

International Journal of Parallel, Emergent and Distributed Systems
Dual-channel binary-countdown medium access control in wireless network-on-chip

Proceedings of the 2nd international conference on Nano-Networks
Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support

Proceedings of the 2nd international conference on Nano-Networks
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Proceedings of the 2nd international conference on Nano-Networks
QNoC asynchronous router

Integration, the VLSI Journal
Link-load balance aware mapping and routing for NoC

WSEAS Transactions on Circuits and Systems
Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms

OPODIS '08 Proceedings of the 12th International Conference on Principles of Distributed Systems
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

Microprocessors & Microsystems
In-Network Caching for Chip Multiprocessors

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
A voltage-frequency island aware energy optimization framework for networks-on-chip

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ROAdNoC: runtime observability for an adaptive network on chip architecture

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Integrated code and data placement in two-dimensional mesh based chip multiprocessors

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Frequent value compression in packet-based NoC architectures

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Robust concurrent online testing of network-on-chip-based SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MTNet: design of a wireless test framework for heterogeneous nanometer systems-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A flexible framework for communication evaluation in SoC design

International Journal of Parallel Programming
Adaptive data compression for high-performance low-power on-chip networks

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs

IEICE - Transactions on Information and Systems
End-to-end delays in polling tree networks

Proceedings of the 3rd International Conference on Performance Evaluation Methodologies and Tools
Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic

Proceedings of the 2nd International Conference on Simulation Tools and Techniques
A comprehensive power-performance model for NoCs with multi-flit channel buffers

Proceedings of the 23rd international conference on Supercomputing
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of an interconnect architecture and signaling technology for parallelism in communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability of network topologies in FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reactive NUCA: near-optimal block placement and replication in distributed caches

Proceedings of the 36th annual international symposium on Computer architecture
Firefly: illuminating future network-on-chip with nanophotonics

Proceedings of the 36th annual international symposium on Computer architecture
Type-Directed Compilation for Multicore Programming

Electronic Notes in Theoretical Computer Science (ENTCS)
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
A variable frequency link for a power-aware network-on-chip (NoC)

Integration, the VLSI Journal
Slotless module-based reconfiguration of embedded FPGAs

ACM Transactions on Embedded Computing Systems (TECS)
A packet-switched network architecture for reconfigurable computing

ACM Transactions on Embedded Computing Systems (TECS)
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Fault-tolerant architecture and deflection routing for degradable NoC switches

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
CTC: An end-to-end flow control protocol for multi-core systems-on-chip

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Scalability of network-on-chip communication architecture for 3-D meshes

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Connection-centric network for spiking neural networks

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring concentration and channel slicing in on-chip network router

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Journal of Signal Processing Systems
An Advanced NoP Selection Strategy for Odd-Even Routing Algorithm in Network-on-Chip

ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Power optimization for application-specific networks-on-chips: A topology-based approach

Microprocessors & Microsystems
Performance analysis of small non-uniform packet switches

Performance Evaluation
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Journal of Systems Architecture: the EUROMICRO Journal
Exposing non-standard architectures to embedded software using compile-time virtualisation

CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Automated technique for design of NoC with minimal communication latency

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
An SDRAM-aware router for Networks-on-Chip

Proceedings of the 46th Annual Design Automation Conference
Model Based Testing of a Network-on-Chip Component

Electronic Notes in Theoretical Computer Science (ENTCS)
Design and management of voltage-frequency island partitioned networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom networks-on-chip architectures with multicast routing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high level power model for Network-on-Chip (NoC) router

Computers and Electrical Engineering
A networks-on-chip architecture design space exploration - The LIB

Computers and Electrical Engineering
A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

Computers and Electrical Engineering
Router designs for elastic buffer on-chip networks

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Allocator implementations for network-on-chip routers

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for constraint-driven synthesis of on-chip communications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An outlook on design technologies for future integrated systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A DAMQ shared buffer scheme for network-on-chip

CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A system-level design methodology for application-specific networks-on-chip

Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support

Proceedings of the 6th FPGAworld Conference
Low-cost router microarchitecture for on-chip networks

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
An accurate and efficient performance analysis approach based on queuing model for Network on Chip

Proceedings of the 2009 International Conference on Computer-Aided Design
A performance analytical model for Network-on-Chip with constant service time routers

Proceedings of the 2009 International Conference on Computer-Aided Design
A method for calculating hard QoS guarantees for Networks-on-Chip

Proceedings of the 2009 International Conference on Computer-Aided Design
An analytical performance model for the Spidergon NoC with virtual channels

Journal of Systems Architecture: the EUROMICRO Journal
Approximation of discrete-time polling systems via structured Markov chains

Proceedings of the Fourth International ICST Conference on Performance Evaluation Methodologies and Tools
Challenging VMs on battery-powered embedded devices

Proceedings of the Third Workshop on Virtual Machines and Intermediate Languages
Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FinFET-based power simulator for interconnection networks

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Predicting the performance of application-specific NoCs implemented on FPGAs

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Physical synthesis of bus matrix for high bandwidth low power on-chip communications

Proceedings of the 19th international symposium on Physical design
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints

ACM Transactions on Architecture and Code Optimization (TACO)
Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching

ACM Transactions on Architecture and Code Optimization (TACO)
An analysis of on-chip interconnection networks for large-scale chip multiprocessors

ACM Transactions on Architecture and Code Optimization (TACO)
Building asynchronous routers with independent sub-channels

SOC'09 Proceedings of the 11th international conference on System-on-chip
On a web-graph-based micronetwork architecture for SoCs

International Journal of Computers and Applications
Scalability of relaxed consistency models in NoC based multicore architectures

ACM SIGARCH Computer Architecture News
Compiler directed network-on-chip reliability enhancement for chip multiprocessors

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
A multiprocessor cache for massively parallel soc architectures

ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Partially reconfigurable point-to-point interconnects in Virtex-II pro FPGAs

ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Formal models for multicast traffic in network on chip architectures with compositional high-level Petri nets

ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
THIN: a new hierarchical interconnection network-on-chip for SOC

ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
A routing algorithm for random error tolerance in network-on-chip

HCI'07 Proceedings of the 12th international conference on Human-computer interaction: applications and services
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints

Proceedings of the 2010 ACM Symposium on Applied Computing
A generic network interface architecture for a networked processor array (NePA)

ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
The SKB: a semi-completely-connected bus for on-chip systems

NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
A novel congestion control scheme for elastic flows in network-on-chip based on sum-rate optimization

ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
A low-overhead and reliable switch architecture for Network-on-Chips

Integration, the VLSI Journal
An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip

International Journal of High Performance Systems Architecture
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

International Journal of High Performance Systems Architecture
Future of interconnect fabric: a contrarian view

Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Supporting islands of coherency for highly-parallel embedded architectures using compile-time virtualisation

Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Communication modeling of multicast in all-port wormhole-routed NoCs

Journal of Systems and Software
EDXY - A low cost congestion-aware routing algorithm for network-on-chips

Journal of Systems Architecture: the EUROMICRO Journal
Software defined radio architecture using a multicasting network-on-chip

ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
A flexible parallel simulator for networks-on-chip with error control

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluating Bufferless Flow Control for On-chip Networks

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Low-Latency and Memory-Efficient On-chip Network

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Network-on-Chip Architectures for Neural Networks

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Hierarchical Network-on-Chip for Embedded Many-Core Architectures

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Fault tolerant network on chip switching with graceful performance degradation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design

Journal of Signal Processing Systems
Self-adaptive system for addressing permanent errors in on-chip interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate predictive interconnect modeling for system-level design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complement routing: A methodology to design reliable routing algorithm for Network on Chips

Microprocessors & Microsystems
A fuzzy-based power-aware routing algorithm for network on chip

ICACT'10 Proceedings of the 12th international conference on Advanced communication technology
UNION: a unified inter/intra-chip optical network for chip multiprocessors

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Networks on Chips: from research to products

Proceedings of the 47th Design Automation Conference
Trace-driven optimization of networks-on-chip configurations

Proceedings of the 47th Design Automation Conference
Distributed task migration for thermal management in many-core systems

Proceedings of the 47th Design Automation Conference
Energy efficient mapping and voltage islanding for regular NoC under design constraints

International Journal of High Performance Systems Architecture
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

Microelectronics Journal
PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems

Microelectronics Journal
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal
Proximity coherence for chip multiprocessors

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Moths: mobile threads for on-chip networks

Proceedings of the 19th international conference on Parallel architectures and compilation techniques
A data capturing method for buses on chip

IEEE Transactions on Circuits and Systems Part I: Regular Papers
What is a 3D Network-on-Chip?

ACM SIGDA Newsletter
An overview of achieving energy efficiency in on-chip networks

International Journal of Communication Networks and Distributed Systems
Designing heterogeneous embedded network-on-chip platforms with users in mind

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical multi-agent protection system for NoC based MPSoCs

Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems
Next generation on-chip networks: what kind of congestion control do we need?

Hotnets-IX Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks
An efficient distributed memory interface for many-core platform with 3D stacked DRAM

Proceedings of the Conference on Design, Automation and Test in Europe
Accelerating lightpath setup via broadcasting in binary-tree waveguide in optical NoCs

Proceedings of the Conference on Design, Automation and Test in Europe
Feedback control for providing QoS in NoC based multicores

Proceedings of the Conference on Design, Automation and Test in Europe
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors

Proceedings of the Conference on Design, Automation and Test in Europe
Formal specification of networks-on-chips: deadlock and evacuation

Proceedings of the Conference on Design, Automation and Test in Europe
Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip

Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Hardware trust implications of 3-D integration

WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Enhancing network-on-chip components to support security of processing elements

WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe
Priority-based packet communication on a bus-shaped structure for FPGA-systems

Proceedings of the Conference on Design, Automation and Test in Europe
Configurable links for runtime adaptive on-chip communication

Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of low-overhead configurable source routing tables for network interfaces

Proceedings of the Conference on Design, Automation and Test in Europe
SCORES: a scalable and parametric streams-based communication architecture for modular reconfigurable systems

Proceedings of the Conference on Design, Automation and Test in Europe
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

Proceedings of the Conference on Design, Automation and Test in Europe
MPSoCs run-time monitoring through networks-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe
aEqualized: a novel routing algorithm for the Spidergon network on chip

Proceedings of the Conference on Design, Automation and Test in Europe
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes

Proceedings of the Conference on Design, Automation and Test in Europe
Asynchronous current mode serial communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
An SDRAM-aware router for networks-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Exploring programming model-driven QoS support for NoC-based platforms

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A methodology for design of unbuffered router microarchitecture for S-mesh NoC

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Convex-based DOR routing for virtualization of NoC

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
ERA: an efficient routing algorithm for power, throughput and latency in network-on-chips

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Weighted random oblivious routing on torus networks

Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
An analytical model of broadcast in QoS-aware wormhole-routed NoCs

Journal of Systems and Software
A low-area multi-link interconnect architecture for GALS chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs

Integration, the VLSI Journal
State observer controller design for packets flow control in networks-on-chip

The Journal of Supercomputing
Schedulability analysis and task mapping for real-time on-chip communication

Real-Time Systems
Embedded network protocols for mobile devices

FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
Reliable network-on-chip design for multi-core system-on-chip

The Journal of Supercomputing
Improved on-chip router analytical power and area modeling

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A low latency wormhole router for asynchronous on-chip networks

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Application-specific 3D Network-on-Chip design using simulated allocation

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Area and power-efficient innovative congestion-aware Network-on-Chip architecture

Journal of Systems Architecture: the EUROMICRO Journal
Modeling and evaluation of ring-based interconnects for Network-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs

Journal of Systems Architecture: the EUROMICRO Journal
Network-on-Chip interconnect for pairing-based cryptographic IP cores

Journal of Systems Architecture: the EUROMICRO Journal
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture

Proceedings of the Third International Workshop on Network on Chip Architectures
An analytical approach for network-on-chip performance analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A networks-on-chip emulation/verification framework

International Journal of High Performance Systems Architecture
An improved algorithm for slot selection in the Æthereal network-on-chip

Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

Microprocessors & Microsystems
A NoC-based hybrid message-passing/shared-memory approach to CMP design

Microprocessors & Microsystems
Asynchronous spatial division multiplexing router

Microprocessors & Microsystems
A hardwired NoC infrastructure for embedded systems on FPGAs

Microprocessors & Microsystems
Scalable network-on-chip architecture for configurable neural networks

Microprocessors & Microsystems
A TDM slot allocation flow based on multipath routing in NoCs

Microprocessors & Microsystems
Virtualizing network-on-chip resources in chip-multiprocessors

Microprocessors & Microsystems
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture

Microprocessors & Microsystems
On chip interconnects for multiprocessor turbo decoding architectures

Microprocessors & Microsystems
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips

Journal of Computer Science and Technology
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip

Proceedings of the 16th Asia and South Pacific Design Automation Conference
On the design and analysis of fault tolerant NoC architecture using spare routers

Proceedings of the 16th Asia and South Pacific Design Automation Conference
A resilient on-chip router design through data path salvaging

Proceedings of the 16th Asia and South Pacific Design Automation Conference
NS-FTR: a fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Scalable and cost-effective interconnection of data-center servers using dual server ports

IEEE/ACM Transactions on Networking (TON)
An analytical model for Network-on-Chip with finite input buffer

Frontiers of Computer Science in China
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans

International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
A workload-adaptive and reconfigurable bus architecture for multicore processors

International Journal of Reconfigurable Computing
Efficient synchronization for embedded on-chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
"It's a small world after all": noc performance optimization via long-range link insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of network-on-chip architectures with a genetic algorithm-based technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAFES: A framework for intrachip application modeling and communication architecture design

Journal of Parallel and Distributed Computing
An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation

ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
A learning-based approach to the automated design of MPSoC networks

ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Hardware-enabled dynamic resource allocation for manycore systems using bidding-based system feedback

EURASIP Journal on Embedded Systems
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling

Microelectronics Journal
GNLS: a hybrid on-chip communication architecture for SoC designs

International Journal of High Performance Systems Architecture
Low-power, high-speed transceivers for network-on-chip communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-CMP system with data communication on the fly

The Journal of Supercomputing
Automatic verification for deadlock in Networks-on-Chips with adaptive routing and wormhole switching

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Prevention flow-control for low latency torus Networks-on-Chip

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
DART: a programmable architecture for NoC simulation on FPGAs

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
VLSI micro-architectures for high-radix crossbar schedulers

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Reducing Network-on-Chip energy consumption through spatial locality speculation

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Proceedings of the 38th annual international symposium on Computer architecture
A case for globally shared-medium on-chip interconnect

Proceedings of the 38th annual international symposium on Computer architecture
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees

Proceedings of the 38th annual international symposium on Computer architecture
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip

Proceedings of the 38th annual international symposium on Computer architecture
Cluster-based application mapping method for Network-on-Chip

Advances in Engineering Software
A 98 GMACs/W 32-core vector processor in 65nm CMOS

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Performance evaluation of a wormhole-routed algorithm for irregular mesh NoC interconnect

ICDCN'10 Proceedings of the 11th international conference on Distributed computing and networking
Process variation-aware routing in NoC based multicores

Proceedings of the 48th Design Automation Conference
FlexiBuffer: reducing leakage power in on-chip network routers

Proceedings of the 48th Design Automation Conference
Capacity optimized NoC for multi-mode SoC

Proceedings of the 48th Design Automation Conference
Optimal memory controller placement for chip multiprocessor

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A saturated tree network of polling stations with flow control

Proceedings of the 23rd International Teletraffic Congress
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation

ACM Transactions on Embedded Computing Systems (TECS)
Energy characteristic of a processor allocator and a network-on-chip

International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
A study of 3D Network-on-Chip design for data parallel H.264 coding

Microprocessors & Microsystems
Adaptive inter-layer message routing in 3D networks-on-chip

Microprocessors & Microsystems
Analytical derivation of traffic patterns in cache-coherent shared-memory systems

Microprocessors & Microsystems
Service based communication for MPSoC platform-SegBus

Microprocessors & Microsystems
Asynchronous switching for low-power networks-on-chip

Microelectronics Journal
3D NOC for many-core processors

Microelectronics Journal
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures

ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the use of multiplanes on a 2D mesh network-on-chip

ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs

Proceedings of the 4th International Workshop on Network on Chip Architectures
Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing

Proceedings of the 4th International Workshop on Network on Chip Architectures
Throughput aware mapping for network on chip design of h.264 decoder

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

ACM Journal on Emerging Technologies in Computing Systems (JETC)
GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Buffered deflection routing for networks-on-chip

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Efficient switches for network-on-chip based embedded systems

EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Co-design of channel buffers and crossbar organizations in NoCs architectures

Proceedings of the International Conference on Computer-Aided Design
A tree-based topology synthesis for on-chip network

Proceedings of the International Conference on Computer-Aided Design
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations

Proceedings of the International Conference on Computer-Aided Design
System interconnect design exploration for embedded MPSoCs

Proceedings of the System Level Interconnect Prediction Workshop
Computing platforms

Embedded Systems Design
A multi-level design methodology of multistage interconnection network for MPSOCs

International Journal of Computer Applications in Technology
Network-on-Chip routing algorithms by breaking cycles

ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Making-a-stop: A new bufferless routing algorithm for on-chip network

Journal of Parallel and Distributed Computing
PSK signalling on noc buses

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
The NoX router

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Packet chaining: efficient single-cycle allocation for on-chip networks

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A data layout optimization framework for NUCA-based multicores

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Hunting deadlocks efficiently in microarchitectural models of communication fabrics

Proceedings of the International Conference on Formal Methods in Computer-Aided Design
A NoC system generator for the Sea-of-Cores era

Proceedings of the 8th FPGAWorld Conference
Optimized 3D Network-on-Chip Design Using Simulated Allocation

ACM Transactions on Design Automation of Electronic Systems (TODAES)
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip

Computers and Electrical Engineering
A fault tolerant approach to object oriented design and synthesis of embedded systems

LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
A method for router table compression for application specific routing in mesh topology noc architectures

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Adaptive coding in networks-on-chip: transition activity reduction versus power overhead of the codec circuitry

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
The optimum network on chip architectures for video object plane decoder design

ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
Enforcing dimension-order routing in on-chip torus networks without virtual channels

ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
Neighborhood-aware data locality optimization for NoC-based multicores

CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Towards the formal verification of cache coherency at the architectural level

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
A3MAP: Architecture-aware analytic mapping for networks-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Networks on chips: structure and design methodologies

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Status data and communication aspects in dynamically clustered network-on-chip monitoring

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Proceedings of the 49th Annual Design Automation Conference
A hybrid NoC design for cache coherence optimization for chip multiprocessors

Proceedings of the 49th Annual Design Automation Conference
Exploration of heuristic scheduling algorithms for 3D multicore processors

Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
A greedy heuristic approximation scheduling algorithm for 3d multicore processors

Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing
Study of hierarchical n-body methods for network-on-chip architectures

Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing - Volume 2
CRAIS: a crossbar based adaptive interconnection scheme

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture

Computers and Electrical Engineering
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison

International Journal of High Performance Systems Architecture
High-throughput differentiated service provision router architecture for wireless network-on-chip

International Journal of High Performance Systems Architecture
t(k)-SA: accelerated simulated annealing algorithm for application mapping on networks-on-chip

Proceedings of the 14th annual conference on Genetic and evolutionary computation
Enhancing effective throughput for transmission line-based bus

Proceedings of the 39th Annual International Symposium on Computer Architecture
An evaluation of an integrated on-chip/off-chip network for high-performance reconfigurable computing

International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
On-chip networks from a networking perspective: congestion and scalability in many-core interconnects

Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Microprocessors & Microsystems
Handling global traffic in future CMP NoCs

Proceedings of the International Workshop on System Level Interconnect Prediction
A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems

Journal of Parallel and Distributed Computing
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms

Microprocessors & Microsystems
Power-efficient deterministic and adaptive routing in torus networks-on-chip

Microprocessors & Microsystems
APCR: an adaptive physical channel regulator for on-chip interconnects

Proceedings of the 21st international conference on Parallel architectures and compilation techniques
On-chip networks from a networking perspective: congestion and scalability in many-core interconnects

ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Concerning with on-chip network features to improve cache coherence protocols for CMPs

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Performance and complexity analysis of credit-based end-to-end flow control in network-on-chip

ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors

ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
A high-efficiency low-cost heterogeneous 3D network-on-chip design

Proceedings of the Fifth International Workshop on Network on Chip Architectures
Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip

Journal of Parallel and Distributed Computing
A survey on application mapping strategies for Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
Parameter-optimized simulated annealing for application mapping on networks-on-chip

LION'12 Proceedings of the 6th international conference on Learning and Intelligent Optimization
Accurate on-chip router area modeling with kriging methodology

Proceedings of the International Conference on Computer-Aided Design
TRACKER: a low overhead adaptive NoC router with load balancing selection strategy

Proceedings of the International Conference on Computer-Aided Design
Cost evaluation on reuse of generic network service dies in three-dimensional integrated circuits

Microelectronics Journal
Moths: Mobile threads for on-chip networks

ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Performance Analysis of On-Chip Communication Structures under Device Variability

International Journal of Embedded and Real-Time Communication Systems
Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs

International Journal of Embedded and Real-Time Communication Systems
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable load balancing congestion-aware Network-on-Chip router architecture

Journal of Computer and System Sciences
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

Journal of Computer and System Sciences
Efficient genetic based topological mapping using analytical models for on-chip networks

Journal of Computer and System Sciences
Physical-aware system-level design for tiled hierarchical chip multiprocessors

Proceedings of the 2013 ACM international symposium on International symposium on physical design
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Addressing End-to-End Memory Access Latency in NoC-Based Multicores

MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Software-defined massive multicore networking via freespace optical interconnect

Proceedings of the ACM International Conference on Computing Frontiers
A source-synchronous Htree-based network-on-chip

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Switch folding: network-on-chip routers with time-multiplexed output ports

Proceedings of the Conference on Design, Automation and Test in Europe
Wireless interconnect for board and chip level

Proceedings of the Conference on Design, Automation and Test in Europe
Exploring topologies for source-synchronous ring-based network-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe
40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS

Proceedings of the Conference on Design, Automation and Test in Europe
Designing energy-efficient NoC for real-time embedded systems through slack optimization

Proceedings of the 50th Annual Design Automation Conference
Smart hill climbing for agile dynamic mapping in many-core systems

Proceedings of the 50th Annual Design Automation Conference
21st century digital design tools

Proceedings of the 50th Annual Design Automation Conference
A multi-agent framework for thermal aware task migration in many-core systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-layer adaptive error control for network-on-chip links

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip network fabric supporting coarse-grained processor array

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level modeling and analysis of thermal effects in optical networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New heuristic algorithms for low-energy mapping and routing in 3D NoC

International Journal of Computer Applications in Technology
Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A TDM NoC supporting QoS, multicast, and fast connection set-up

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A fast, source-synchronous ring-based network-on-chip design

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
An energy-aware online task mapping algorithm in NoC-based system

The Journal of Supercomputing
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems

Journal of Systems Architecture: the EUROMICRO Journal
NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures

Journal of Systems Architecture: the EUROMICRO Journal
Application-Specific Network-on-Chip synthesis with flexible router Placement

Journal of Systems Architecture: the EUROMICRO Journal
Optimal placement of vertical connections in 3D Network-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs

Journal of Systems Architecture: the EUROMICRO Journal
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Journal of Systems Architecture: the EUROMICRO Journal
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors

The Journal of Supercomputing
Scalable high-radix router microarchitecture using a network switch organization

ACM Transactions on Architecture and Code Optimization (TACO)
Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect

PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

Parallel Computing
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh

ACM Transactions on Design Automation of Electronic Systems (TODAES)
User satisfaction aware routing decisions in NOC

Proceedings of the Sixth International Workshop on Network on Chip Architectures
Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth

Proceedings of the Sixth International Workshop on Network on Chip Architectures
An analytical model for on-chip interconnects in multimedia embedded systems

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe

International Journal of Embedded and Real-Time Communication Systems
Multi-hop communications on wireless network-on-chip using optimized phased-array antennas

Computers and Electrical Engineering
Use it or lose it: wear-out and lifetime in future chip multiprocessors

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems

ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

Wireless Personal Communications: An International Journal
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial)

Proceedings of the International Conference on Computer-Aided Design
Non-minimal, turn-model based NoC routing

Microprocessors & Microsystems
Direct distributed memory access for CMPs

Journal of Parallel and Distributed Computing
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

Microprocessors & Microsystems
Design and implementation of a network on chip-based simulator: a performance study

International Journal of Computational Science and Engineering
TM: a new and simple topology for interconnection networks

The Journal of Supercomputing
Asymmetrical topology and entropy-based heterogeneous link for many-core massive data communication

Cluster Computing
A Fault Tolerant Hierarchical Network on Chip Router Architecture

Journal of Electronic Testing: Theory and Applications
High-speed dynamic TDMA arbiter for inter-layer communications in 3-D network-on-chip

Journal of High Speed Networks

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Abstract

Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.