Energy characteristic of a processor allocator and a network-on-chip

  • Authors:

  • Dawid Zydek;Henry Selvaraj;Grzegorz Borowik;Tadeusz ŁUba

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, 4505 S. Maryland Parkway, Las Vegas, NV 89154-4026, USA;Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, 4505 S. Maryland Parkway, Las Vegas, NV 89154-4026, USA;Institute of Telecommunications Warsaw, University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland;Institute of Telecommunications Warsaw, University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland

  • Venue:
  • International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
  • Year:
  • 2011

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Abstract

Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.