Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
An Efficient Task Allocation Scheme for 2D Mesh Architectures
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
A fast and efficient processor management scheme for k-ary n-cubes1
Journal of Parallel and Distributed Computing
An Efficient Recognition-Complete Processor Allocation Strategy for k-ary n-cube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers
IEEE Transactions on Computers
A Top-Down Processor Allocation Scheme for Hypercube Computers
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Comments on "A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers"
IEEE Transactions on Computers
Efficient processor allocation for 3D tori
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
An efficient free-list submesh allocation scheme for two-dimensional mesh-connected multicomputers
Journal of Systems and Software
An Adaptive Submesh Allocation Strategy for Two-Dimensional Mesh Connected Systems
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 02
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Processor Allocation Problem for NoC-Based Chip Multiprocessors
ITNG '09 Proceedings of the 2009 Sixth International Conference on Information Technology: New Generations
Energy characteristic of a processor allocator and a network-on-chip
International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
Computers and Electrical Engineering
Bisection (band)width of product networks with application to data centers
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
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Processor Allocator (PA) is a crucial factor in modern Chip MultiProcessors (CMPs). A modern CMP uses Network on Chip (NoC) as communication technique between cores. Thus, the topology of the implemented NoC has also significant impact on the CMP's performance. A good processor allocation technique needs to be fast and ensure the highest possible system utilization. In this paper, we propose a processor allocation technique for such an efficient and fast PA. The PA is driven by a Bit Map Allocation for Torus (BMAT) algorithm, which is a technique designed for k-ary 2-cube topology. The proposed BMAT scheme is presented and described along with a new Busy List Allocation for Torus (BLAT), Sorting Allocation for Torus (SAT) and Stack Based Allocation for Torus (SBAT) algorithms. The presented techniques are compared with previously known important schemes for k-ary 2-mesh topology. The research ideas have been verified using experiments that have also been described in the paper. The presented simulation results reveal that the proposed processor allocation algorithm for k-ary 2-cube, as a technique for PA, achieves better allocation time than all other existing algorithms while the CMP with such a PA is characterized by very high system utilization.