Proceedings of the 6th international workshop on Hardware/software codesign
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FSMD functional partitioning for low power
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low-power task scheduling for multiple devices
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Function and Architecture Optimization and Co-Design of Embedded Systems
Function and Architecture Optimization and Co-Design of Embedded Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient Power Estimation Techniques for HW/SW Systems
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FSM re-engineering and its application in low power state encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploring "temperature-aware" design in low-power MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HybDTM: a coordinated hardware-software approach for dynamic thermal management
Proceedings of the 43rd annual Design Automation Conference
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Power distribution paths in 3-D ICS
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Feedback control for providing QoS in NoC based multicores
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
Fast and efficient processor allocation algorithm for torus-based chip multiprocessors
Computers and Electrical Engineering
Computers and Electrical Engineering
Architectural synthesis for DSP silicon compilers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper looks at the highest design level and presents a methodology for designing Systems On Chip (SOC) with low energy dissipation. The aim is achieved through a functional decomposition of the system, followed by an appropriate allocation of tasks to the different components of the system (ASICs and processors). With our approach, it is possible to generate architectures with different features (time and energy), which allows the designer to fastly obtain the architecture that best suits his application.