Supporting system-level power exploration for DSP applications
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Fast cache and bus power estimation for parameterized system-on-a-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Speeding up power estimation of embedded software
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Designing Energy-Efficient Software
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Cache Optimization For Embedded Processor Cores: An Analytical Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytical Design Space Exploration of Caches for Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cache optimization for embedded processor cores: An analytical approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-time energy estimation in system-on-a-chip designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Efficient voltage scheduling and energy-aware co-synthesis for real-time embedded systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
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We present a power estimation framework for hardware/software System-On-Chip (SOC) designs based on concurrent and synchronized execution of a hardware simulator and an instruction set simulator. Concurrent execution of the simulators for different parts of the system is necessary to obtain accurate input and execution traces, and hence accurate power estimates. However, as in the case of hardware/software co-simulation, the communication and synchronization between the various simulators causes significant overhead. We describe two speedup techniques for addressing this issue energy caching and power macromodeling that present interesting accuracy vs. efficiency tradeoffs.