Low-power architectural design methodologies
Low-power architectural design methodologies
Proceedings of the 6th international workshop on Hardware/software codesign
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
LEneS: task scheduling for low-energy systems using variable supply voltage processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the 14th international symposium on Systems synthesis
Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing
IEEE Transactions on Parallel and Distributed Systems
Hardware/Software Codesign and Rapid Prototyping of Embedded Systems
IEEE Design & Test
System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
An evolutionary approach to system-level synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Efficient Power Estimation Techniques for HW/SW Systems
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
Energy-aware system design with SDL
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
Model-driven development of time-critical protocols with SDL-MDD
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
Near optimal and energy-efficient scheduling for hard real-time embedded systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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This paper presents an integrated methodology and a tool for system-level low power/energy co-synthesis for real-time embedded systems. Voltage scheduling (VS) is being applied to utilize the inherent slacks in the system. The voltage schedule is generated based on a global view of all tasks’ mapping and their energy profiles. The tool explores the three dimensional design space (performance-power-cost) to find implementations that offer the best trade-off among these design objectives. Unnecessary power dissipation is prevented by refining the allocation/binding in an additional synthesis step. The experimental results show that our approach remarkably improves the efficiency of VS and leads to additional energy savings, especially for applications with stringent delay constraints.