An evolutionary approach to system-level synthesis

Authors:
J. Teich;T. Blickle;L. Thiele
Affiliations:
Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH), CH-8092 Zürich, Switzerland;Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH), CH-8092 Zürich, Switzerland;Computer Engineering and Communication Networks Lab (TIK), Swiss Federal Institute of Technology (ETH), CH-8092 Zürich, Switzerland
Venue:
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Year:
1997

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Abstract

Considers system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires: (1) the selection of the architecture (allocation), including general-purpose and dedicated processors, ASICs, buses and memories; (2) the mapping of the algorithm onto the selected architecture in space (binding) and time (scheduling); and (3) the design space exploration, with the goal of finding a set of implementations that satisfy a number of constraints on cost and performance. In this paper, a new graph-based mapping model is introduced to specify the task of system-level synthesis as an optimization problem. An evolutionary algorithm is adapted to solve this problem and is applied to explore the design space of video-codec implementations.