Target architecture oriented high-level synthesis for multi-FPGA based emulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An evolutionary approach to system-level synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Rapid Synthesis of Multi-Chip Systems
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraint-driven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology.