The effects of physical design characteristics on the area-performance tradeoff curve
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Specification and design of embedded systems
Specification and design of embedded systems
A methodology and design tools to support system-level VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
High-Level VLSI Synthesis
Accurate area and delay estimation from RTL descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performance-driven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration flow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.