Computer system architecture (3rd ed.)
Computer system architecture (3rd ed.)
An object-oriented, procedural database for VLSI chip planning
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Design and Analysis of Instruction Set Processors
Design and Analysis of Instruction Set Processors
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Register-transfer level digital design automation: The allocation process
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '78 Proceedings of the 15th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Compiling pascal programs into silicon (design automation, hardware synthesis)
Compiling pascal programs into silicon (design automation, hardware synthesis)
The VLSI Design Automation Assistant: From Algorithms to Silicon
IEEE Design & Test
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Anatomy of a hardware compiler
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The MICON system for computer design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A note on clustering modules for floorplanning
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A technology-adaptive allocation of functional units and connections
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Global hardware synthesis from behavioral dataflow descriptions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: technology transfer to industry
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The effects of physical design characteristics on the area-performance tradeoff curve
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Relevant issues in high-level connectivity synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Bottom up synthesis based on fuzzy schedules
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Constrained register allocation in bus architectures
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Architectural partitioning of control memory for application specific programmable processors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False path exclusion in delay analysis of RTL-based datapath-controller designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Timing estimation for behavioral descriptions
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Controller and datapath trade-offs in hierarchical RT-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Interconnection synthesis with geometric constraints
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VLSI design synthesis with testability
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A graphical hardware design language
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An object-oriented, procedural database for VLSI chip planning
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
IEEE Design & Test
Design Synthesis and Silicon Compilation
IEEE Design & Test
A Model-Based Expert System for Digital System Design
IEEE Design & Test
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An evolutionary approach to system-level synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Redesign using state splitting
EURO-DAC '90 Proceedings of the conference on European design automation
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Datapath optimization using feedback
EURO-DAC '91 Proceedings of the conference on European design automation
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages
The Journal of Supercomputing
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Integration, the VLSI Journal
Attributes of industrial machine and process control systems
International Journal of Computer Applications in Technology
Design methodologies and CAD tools
Integration, the VLSI Journal
Optimal synthesis of control logic from behavioral specifications
Integration, the VLSI Journal
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper reports on a new method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral descriptions. There are two important ways in which this method differs from traditional top-down synthesis techniques. First, it draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design. Second, it uses a different method for representing and organizing knowledge about a design that makes possible estimates of physical placement and wiring in the analysis of that design, even at the abstract register-transfer level. This allows a more accurate evaluation of candidate register-transfer designs without doing a full logic-level or transistor-level layout. It also leads to a simple method for systematically exploring the space of possible designs in order to find the one that best meets the designer's objectives and constraints.