Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Artificial intelligence
Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Knowledge based control in micro-architecture design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ISIS: a system for performance driven resource sharing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
EURO-DAC '92 Proceedings of the conference on European design automation
System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Deriving efficient area and delay estimates by modeling layout tools
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An approximate timing analysis method for datapath circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Timing estimation for behavioral descriptions
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Exact required time analysis via false path detection
DAC '97 Proceedings of the 34th annual Design Automation Conference
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing analysis in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Datapath optimization using feedback
EURO-DAC '91 Proceedings of the conference on European design automation
Quadratic zero-one programming-based synthesis of application-specific data paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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In this paper, we present an accurate delay-estimation algorithm at the register-transfer level. We study three important sources of false paths in register-transfer-level (RTL) structures, i.e., 1) resource binding; 2) interdependent conditions; and 3) datapath-controller path mismatching. The existence and creation of such paths and their effects in delay analysis are discussed. We show that in a RTL datapath structure the accuracy of the delay estimators is affected by the existence of false paths. Specifically, the accuracy drops significantly for structures synthesized from condition-dominated behaviors. We will propose a mechanism to efficiently avoid false paths in delay analysis. This is achieved by introducing the propagation delay graph (PDG), whose traversal for delay analysis is equivalent to the traversal of sensitizable paths in the datapath. Comparison with the timing verifier in commercial computer-aided design (CAD) tools, show that estimated delays are within 14% accuracy of those reported by CAD tools.