The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
The Verifiacation Problem for Safe Replaceability
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Hierarchical functional timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Detecting false timing paths: experiments on PowerPC microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing-safe false path removal for combinational modules
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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This paper addresses how to compute required times at intermediatenodes in a combinational network given required times atprimary outputs. The simplest approach is to compute them basedon topological delay analysis without any consideration of falsepaths. In this paper, however, we take into account false pathsbetween the intermediate nodes and the primary outputs explicitlyto characterize the timing constraints at the nodes more accurately.We show that this approach leads to a technique for computing amore refined and relaxed timing constraint than that obtained bytopological analysis. We generalize the notion of required timesfrom a single constant to a relation where a signal is required atdifferent times depending on the values of the other signals.