Timing Analysis Using Functional Analysis
IEEE Transactions on Computers
Exact required time analysis via false path detection
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical functional timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing analysis and optimization for high-performance digital circuits
Timing analysis and optimization for high-performance digital circuits
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A false-path aware formal static timing analyzer considering simultaneous input transitions
Proceedings of the 46th Annual Design Automation Conference
On timing-independent false path identification
Proceedings of the International Conference on Computer-Aided Design
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A combinational module is a combinational circuit that can be used under any arrival time condition at the primary inputs. An intellectual property (IP) module, if combinational, is one such example. The false-path-aware delay characterization of a combinational module without disclosing its internal structural detail is crucial for accurate timing analysis of IP-based designs.This paper addresses three related issues on delay characterization of combinational modules. We first introduce a new notion called timing-safe replaceability as a way of comparing the timing characteristics of two combinational modules formally. This notion allows us to determine whether a new module is a safe replacement of an original module under any surrounding environment with respect to timing. Second, we consider false path detection of combinational modules. Although false path detection is essential in accurate delay modeling, we argue that the conventional definition of false paths such as floating mode analysis is not appropriate for defining the falsity of a path for a combinational module since the falsity is relative to an arrival time condition. A new definition of false paths, termed strongly false paths, is introduced to resolve this issue. Strongly false paths are those paths that are guaranteed to be false under any arrival time condition, and thus uniquely defined independent of arrival time conditions. Finally, we propose a new algorithm that removes strongly false paths from a combinational module by a circuit transformation. We prove that the resulting circuit is a timing-safe replacement of the original.