On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Timing-safe false path removal for combinational modules
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
False timing path identification using ATPG techniques and delay-based information
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
Mining Sequential Constraints for Pseudo-Functional Testing
ATS '07 Proceedings of the 16th Asian Test Symposium
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-placement voltage island generation for timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
Clock skew scheduling for timing speculation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper is concerned with finding timing-independent false paths that cannot be sensitized under any signal arrival time condition in integrated circuits. Existing techniques regard a path as a true path as long as a vector pair can be found to sensitize it. This is rather pessimistic since such a path might be activated only with illegal states in the circuit and hence it is actually functionally-unsensitizable. In this paper, we develop novel techniques to take the above issue into consideration when identifying false paths, which facilitates us to find much more false paths than conventional techniques. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed methodology.