VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Timing analysis based on primitive path delay fault identification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Detecting false timing paths: experiments on PowerPC microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Full chip false timing path identification: applications to the PowerPCTM microprocessors
Proceedings of the conference on Design, automation and test in Europe
Functional timing analysis using ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path selection for monitoring unexpected systematic timing effects
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A false-path aware formal static timing analyzer considering simultaneous input transitions
Proceedings of the 46th Annual Design Automation Conference
On timing-independent false path identification
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
A well-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently [6],[9], as well as how to bridge the gap between the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths [9]. In this paper, we will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PowerPC™.