False timing path identification using ATPG techniques and delay-based information
Proceedings of the 39th annual Design Automation Conference
Test structures for delay variability
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Kernel Methods for Pattern Analysis
Kernel Methods for Pattern Analysis
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
Statistical framework for technology-model-product co-design and convergence
Proceedings of the 44th annual Design Automation Conference
Statistical diagnosis of unmodeled systematic timing effects
Proceedings of the 45th annual Design Automation Conference
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
Proceedings of the 47th Design Automation Conference
Representative path selection for post-silicon timing prediction under variability
Proceedings of the 47th Design Automation Conference
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a novel path selection methodology to select paths for monitoring unexpected systematic timing effects. The methodology consists of three components: path filtering, path encoding, and path clustering. Given a large set of critical paths, in path filtering, the goal is to filter out paths that cannot be functionally sensitized. To explore the space of unexpected timing effects, a set of features are defined to encode paths into path vectors. Each feature is a source of concern that may potentially contribute to the cause of an unexpected timing effect. Finally, a kernel-based clustering algorithm is employed to group similar path vectors into clusters from which the best representative paths are selected for post-silicon monitoring. The effectiveness of our proposed methodology is demonstrated through experiments on an industrial ASIC design.