On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Timing-safe false path removal for combinational modules
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Full chip false timing path identification: applications to the PowerPCTM microprocessors
Proceedings of the conference on Design, automation and test in Europe
False timing path identification using ATPG techniques and delay-based information
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Timing Analysis with Implicitly Specified False Paths
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Improving the efficiency of static timing analysis with false paths
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
A current source model for CMOS logic cells considering multiple input switching and stack effect
Proceedings of the conference on Design, automation and test in Europe
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Timing closure has always been the biggest bottleneck in the modern VLSI design flow. Traditional timing verification techniques such as Static Timing Analysis (STA) are usually too conservative or sometimes too optimistic. This inaccuracy may lead to an unnecessary procrastination of time to market or even silicon failure. It is mainly due to the inability to detect false paths and handle multiple-input-transitioning effects in the timing analysis process. In this paper, we proposed a novel Formal Static Timing Analysis (FSTA) technique which can model the multiple-input transitioning effects, detect the false paths, and generate an input transition pattern for the true critical path at the same time. This is achieved by tightly integrating a state-of-the-art Boolean Satisfiability (SAT) solver with a STA engine, under a specialized multiple-input-transition timing library. Our experiments compare the FSTA engine with the traditional STA and random simulation techniques. The results show that our approach greatly outperforms random simulation while obtaining more accurate timing analysis results than STA.