Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Predicting Performance of Micropipelines Using Charlie Diagrams
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for crosstalk excitation and propagation in VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonlinear driver models for timing and noise analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
A current source model for CMOS logic cells considering multiple input switching and stack effect
Proceedings of the conference on Design, automation and test in Europe
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Worst-case aggressor-victim alignment with current-source driver models
Proceedings of the 46th Annual Design Automation Conference
A false-path aware formal static timing analyzer considering simultaneous input transitions
Proceedings of the 46th Annual Design Automation Conference
A-stable and L-stable high-order integration methods for solving stiff differential equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Current source modeling in the presence of body bias
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Proceedings of the 50th Annual Design Automation Conference
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transistor-level gate model based statistical timing analysis considering correlations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The problem of multiple-input switching (MIS) has been mostly ignored by the timing CAD community. Not modeling MIS for timing can result in as much as 100% error in stage delay and slew calculation. The impact is especially severe on stages immediately after a bank of flops, where the inputs have a high probability of arriving simultaneously. Other problems such as modeling of interconnect loads, complex (nonlinear/non-monotonic) input waveforms, power-droop impact on cell delay, nonlinear input capacitances, delay variations due to cross-capacitance, etc. are also known sources of error. In this paper, we introduce the multi-port current source model (MCSM). MCSM can efficiently handle an arbitrary number of simultaneously switching inputs, including single-input switching (SIS). Moreover, MCSM is comprehensive in that other modeling problems associated with delay and noise computation are elegantly covered. We demonstrate the applicability of MCSM on a large 65 nm industrial test-case. For cells experiencing MIS, the model yields delay and slew-rate errors within ±5% for 88.3% and 93.0% of the cases, respectively. We also present data that show that MCSM is an effective receiver model which captures active loading effects without incurring significant additional error. MCSM makes combined cell-level timing, noise, and power analysis a possibility.