Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Fast statistical circuit analysis with finite-point based transistor model
Proceedings of the conference on Design, automation and test in Europe
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Weibull-based analytical waveform model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
SWAT: simulator for waveform-accurate timing including parameter variations and transistor aging
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Transistor-level gate model based statistical timing analysis considering correlations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-level models for standard cells, which have accuracy problems as well as require massive amounts of CPU time in Monte-Carlo (MC) simulation. In this paper we present a new transistor-level non-Monte Carlo statistical analysis method based on solving random differential equations (RDE) computed from modified nodal analysis (MNA). In order to maintain both high accuracy and efficiency, we introduce a simplified statistical transistor model for 45nm technology and below. The model is combined with our new simulation-like engine which can do both implicit non-MC statistical simulation and deterministic simulation fast and accurately. The statistics of delay and slew are calculated by means of the proposed analysis method. Experiments show the proposed method is both run time efficient and very accurate.