Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Transistor-level timing analysis using embedded simulation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
Weibull-based analytical waveform model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Equation- or table-based gate-levelmodels (GLMs) have been applied in static timing analysis (STA) for decades. In order to evaluate the impact of statistical process variabilities, Monte Carlo (MC) simulations are utilized with GLMs for statistical static timing analysis (SSTA), which requires a massive amount of CPU time. Driven by the challenges associated with CMOS technology scaling to 45nm and below, intensive efforts have been contributed to optimize GLMs for higher accuracy at the expense of enhanced complexity. In order to maintain both accuracy and efficiency at 45nm node and below, in this paper we present a gate model built from a simplified transistor model. Considering the increasing statistical process variabilities, the model is embedded in our new statistical simulation engine, which can do both implicit non-MC statistical as well as deterministic simulations. Results of timing, noise and power grid analysis are presented using a 45nm PTMLP technology.