Stochastic finite elements: a spectral approach
Stochastic finite elements: a spectral approach
An Effective Current Source Cell Model for VDSM Delay Calculation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SWAT: simulator for waveform-accurate timing including parameter variations and transistor aging
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Transistor-level gate model based statistical timing analysis considering correlations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
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Increasing variability in the manufacturing process and growing complexity of the integrated circuits has given rise to many design and verification challenges. Statistical analysis of circuits and current source based gate delay models have started to replace the conventional static timing analysis which uses lookup tables for gate delays. In this paper we develop a statistical current source based gate model. We use accurate analytical models for representing the parameters of the gate model as functions of process parameters. Using the proposed statistical gate model, the gate output signal is generated and modeled as process dependent variational waveform. We present a compact model for representation of the variational signal waveform. The proposed waveform model can accurately generate the signal waveform at any process corner for accurate timing analysis. We generated the prosed model for gates of a 90nm industry library and validated with SPICE simulations. Our model for logic gates and variational waveforms showed very good correlation with SPICE. The maximum error across all validation experiments was close to 3%.