Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transistor-level gate model based statistical timing analysis considering correlations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timing analysis (SSTA) for a new level of efficiency-accuracy tradeoff. Our method is based on (1) a multi-point waveform characterization by signal arrival times at multiple voltage thresholds, (2) a parameterized current source gate model for process variations, (3) a parameterized gate performance model for process and signal waveform variations, and (4) Monte Carlo simulation. Our experimental results show that our proposed gate level statistical simulation achieves orders of magnitude of efficiency improvement based on the constructed gate models, while achieving within 3.91% (9.19%) accuracy in average for the means (standard deviations) of signal arrival times at multiple voltage thresholds.