Monte Carlo methods. Vol. 1: basics
Monte Carlo methods. Vol. 1: basics
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A new approach to the use of satisfiability in false path detection
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Statistical critical path analysis considering correlations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
A framework for accounting for process model uncertainty in statistical static timing analysis
Proceedings of the 44th annual Design Automation Conference
Efficient Monte Carlo based incremental statistical timing analysis
Proceedings of the 45th annual Design Automation Conference
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient statistical analysis of read timing failures in SRAM circuits
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cross entropy minimization for efficient estimation of SRAM failure rate
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Considerable effort has been expended in the electronic design automation community in trying to cope with the statistical timing problem. Most of this effort has been aimed at generalizing the static timing analyzers to the statistical case. On the other hand, detailed transistor-level simulations of the critical paths in a circuit are usually performed at the final stage of performance verification. We describe a transistor-level Monte Carlo (MC) technique which makes final transistor-level timing verification practically feasible. The MC method is used as a golden reference in assessing the accuracy of other timing yield estimation techniques. However, it is generally believed, that it can not be used in practice as it requires too many costly transistor-level simulations. We present a novel approach to constructing an improved MC estimator for timing yield which provides the same accuracy as standard MC but at a cost of much fewer transistor-level simulations. This improved estimator is based on a unique combination of a variance reduction technique, importance sampling, and a cheap but approximate gate delay model. The results we present demonstrate that our improved yield estimator achieves the same accuracy as standard MC at a cost reduction reaching several orders of magnitude.