A new approach to the use of satisfiability in false path detection

Authors:
Felipe S. Marques;Renato P. Ribas;Sachin Sapatnekar;André I. Reis
Affiliations:
Instituto de Informática, UFRGS, Porto Alegre, Brazil;Instituto de Informática, UFRGS, Porto Alegre, Brazil;University of Minnesota, Minneapolis, MN;Instituto de Informática, UFRGS, Porto Alegre, Brazil and University of Minnesota, Minneapolis, MN
Venue:
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Year:
2005

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Abstract

This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.