Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
Path verification using Boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A new approach to the use of satisfiability in false path detection
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents improvements on a previous methodology for false path detection using satisfiability. As the previous methodology, which is referred as node-sat, it is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sets of clauses associated to paths, the node-sat can be more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths, and therefore, a smaller number of satisfiability instances needs to be solved. This number can be reduced even more by considering the circuit topology. Experiments comparing the previous node-sat methodology and the new techniques presented on this paper reveal that the execution time is reduced by 60% on average.