Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing analysis in precharge/unate networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An efficient parallel critical path algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Critical path selection for performance optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Is redundancy necessary to reduce delay
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The role of long and short paths in circuit performance optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Experiments with a performance driven module generator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
EURO-DAC '92 Proceedings of the conference on European design automation
The exact solution of timing verification
EURO-DAC '92 Proceedings of the conference on European design automation
PERFLEX: a performance driven module generator
EURO-DAC '92 Proceedings of the conference on European design automation
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
Dynamical identification of critical paths for iterative gate sizing
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Exact path sensitization in timing analysis
EURO-DAC '94 Proceedings of the conference on European design automation
Path sensitization of combinational circuits and its impact on clocking of sequential systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing analysis based on primitive path delay fault identification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems
Journal of Electronic Testing: Theory and Applications
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Symbolic functional and timing verification of transistor-level circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
AFTA: a formal delay model for functional thinking analysis
Proceedings of the conference on Design, automation and test in Europe
Propagation of last-transition-time constraints in gate-level timing analysis
Proceedings of the conference on Design, automation and test in Europe
Path verification using Boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling
Expert Systems with Applications: An International Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Improvements on the detection of false paths by using unateness and satisfiability
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Testability driven statistical path selection
Proceedings of the 48th Design Automation Conference
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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We consider the elimination of false paths in combinational circuits. We give the single generic algorithm that is used to solve this problem, and demonstrate that it is parameterized by a Boolean function called the sensitization condition. We give two criteria which we argue that a valid sensitization condition must meet, and introduce four conditions that have appeared in the recent literature, of which two meet the criteria and two do not. We then introduce a dynamic programming procedure for the tightest of these conditions, the viability condition, and discuss the integration of all four sensitization conditions in the LLLAMA timing environment. We give results on the IWLS and ISCAS benchmark examples and on carry-bypass adders.