On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An efficient parallel critical path algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Detecting false timing paths: experiments on PowerPC microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
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Fast and correct timing verification is a critical issue in VLSIdesign. Several timing verification algorithms have been proposed in thelast few years. However, due to the huge computation time needed toeliminate false paths, existing algorithms have difficulty in performingtiming verification for large circuits. This paper presents efficientcritical path analysis algorithm based on test pattern generation with a newsensitization criterion. The algorithm does not require generation of a pathlist and elimination of false paths to find out the correct critical path ofthe circuit. The inputs which sensitize the critical path are determined aswell. The efficiency and speed of our algorithm are demonstrated using theISCAS benchmark circuits, and the critical paths are found in vastlyimproved times.