Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
SCALD: Structured Computer-Aided Logic Design
DAC '78 Proceedings of the 15th Design Automation Conference
Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
An experimental system for power/timing optimization of LSI chips
DAC '77 Proceedings of the 14th Design Automation Conference
Statistical failure analysis of system timing
IBM Journal of Research and Development
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A novel approach to accurate timing verification using RTL descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing verification by formal signal interaction modeling in a multi-level timing simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Formal Description and Verification of Hardware Timing
IEEE Transactions on Computers
Basic concepts of timing-oriented design automation for high-performance mainframe computers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
CLOVER: a timing constraints verification system
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
IBM Enterprise System/9000 clock system: a technology and system perspective
IBM Journal of Research and Development
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
A timing analysis algorithm for circuits with level-sensitive latches
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Interface timing verification drives system design
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems
Journal of Electronic Testing: Theory and Applications
On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A path selection algorithm for timing analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On Deducing Timing Constraints in the Verification of Interfaces
Formal Methods in System Design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing analysis in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ACTAS: an accurate timing analysis system for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Development of a timing analysis program for multiple clocked network
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Accuracy management for mixed-mode digital VLSI simulation
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Timed pattern generation for noise-on-delay calculation
Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On the signal bounding problem in timing analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
TA-PSV—Timing Analysis for Partially Specified Vectors
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
Design Methodology for a Large Communication Chip
IEEE Design & Test
Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Formal verification of timing conditions
EURO-DAC '90 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Statistical Gate-Delay Model Considering Intra-Gate Variability
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An interactive system for VLSI chip physical design
IBM Journal of Research and Development
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Improving the efficiency of static timing analysis with false paths
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay optimization of linear depth boolean circuits with prescribed input arrival times
Journal of Discrete Algorithms
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Statistical analysis of circuit timing using majorization
Communications of the ACM - A Blind Person's Interaction with Technology
Timing Arc Based Logic Analysis for false noise reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic design error diagnosis and correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neither produce input patterns like test pattern generators nor require input patterns like traditional simulators. Several programs (described here) operate by tracing paths [P173, WO78, SA81, KA81]. One program [MC80] extends simulation into a pessimistic analyzer not dependent on test patterns. Timing Analysis, a program described recently in [H182a], is designed to analyze the timing of large digital computers and is based, in part, on the concepts disclosed in a patented method [DO81] for determining the extreme characteristics of logic block diagrams. The output of Timing Analysis includes “slack” at each block to provide a measure of the severity of the timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach.