Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
MIXS: A mixed level simulator for large digital system logic verification
DAC '80 Proceedings of the 17th Design Automation Conference
The CMU design automation system: An example of automated data path design
DAC '79 Proceedings of the 16th Design Automation Conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
SABLE: A tool for generating structured, multi-level simulations
DAC '79 Proceedings of the 16th Design Automation Conference
Statistical failure analysis of system timing
IBM Journal of Research and Development
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A path selection algorithm for timing analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
ACTAS: an accurate timing analysis system for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Integrated design system for supercomputer SX-1/SX-2
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Structured design verification: Function and timing
DAC '83 Proceedings of the 20th Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Developments in logic network path delay analysis
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Logic design verification using automated test generation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This paper describes a hierarchical design verification system, consisting of a logic verification subsystem, MIXS (1), a timing verification sybsystem, NELTAS(2), and a hierarchical data base. MIXS is a mixed level simulator, which can handle both functional and chip or gate level models with a unified simulation mechanism based on “node” model concept. NELTAS analizes delay time by tracing logical paths and calculating their media delay time. Both subsystems have hierarchical processing capability.