Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
A logic design front-end for improved engineering productivity
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
Will your bridge stand the load? (Position Paper)
DAC '80 Proceedings of the 17th Design Automation Conference
MIXS: A mixed level simulator for large digital system logic verification
DAC '80 Proceedings of the 17th Design Automation Conference
Design verification system for large-scale LSI designs
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '79 Proceedings of the 16th Design Automation Conference
Can CAD meet the VLSI design problems of the 80's?
DAC '79 Proceedings of the 16th Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Dynamic Functional Testing for VLSI Circuits
IEEE Design & Test
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Changes in the design verification environment brought about by VLSI design considerations are discussed. Multi-level modelling support is now required of efficient, interactive verification tools. The role of logic simulators in this environment is analyzed, especially in early error removal during the design cycle. A logic simulation system, which has been implemented as part of the IBM Design and Verification system, is described here. Particular attention is paid to the key areas of hierarchy in the design description, user interaction, and simulation speed.