Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
User requirements for digital design verification simulators
Proceedings of the Symposium on Design Automation and Microprocessors
Simulation hierarchy for microprocessor design
Proceedings of the Symposium on Design Automation and Microprocessors
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
A comparison of clock pulse and event algorithms for simulation of traffic flow
ACM SIGSIM Simulation Digest
Structured design verification: Function and timing
DAC '83 Proceedings of the 20th Design Automation Conference
Digital system simulation: Current status and future trends or darwin's theory of simulation
DAC '81 Proceedings of the 18th Design Automation Conference
Process oriented logic simulation
DAC '81 Proceedings of the 18th Design Automation Conference
Experience with a high level micromachine simulator
MICRO 12 Proceedings of the 12th annual workshop on Microprogramming
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Advancing circuit complexity in LSI technology has brought about an ever growing need for more powerful Computer Aided Design tools. Verification of an IC design through simulation is mandatory to avoid costly mask iterations and delays in product introduction due to design errors. A gate level simulation is one method for reducing errors in a chip design. However, gate level simulations of large designs are extremely expensive. A high level “black box” or functional simulation gains in efficiency, yet loses accuracy. It is possible to minimize the individual disadvantages of these two approaches with a hierarchical simulator that permits a mixture of the two levels. Further improvement can be realized by incorporating a dual mode (fixed event list/event-driven) scheduler within this hierarchical simulation environment to control more efficiently the model evaluation sequence. This paper describes such a scheduler, and the user interfaces for it.