COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Functional verification of MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On the verification of sequential machines at differing levels of abstraction
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Formal specification and verification of hardware: a comparative case study
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Reasoning about digital systems using temporal logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MC 68020 32-Bit Microprocessor User's Manual
MC 68020 32-Bit Microprocessor User's Manual
Design Verification of the WE 32106 Math Accelerator Unit
IEEE Design & Test
IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
Formal design verification of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Structured design verification: Function and timing
DAC '83 Proceedings of the 20th Design Automation Conference
Functional design verification by multi-level simulation
DAC '84 Proceedings of the 21st Design Automation Conference
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The author discusses the two main problems of dynamic testing (i.e. testing while the simulator is running), namely the design of a high-level vector-generation language and the design of the interface between the vector generator and the simulator. He offers guidelines for designing a high-level vector-generation language as well as several examples written in FHDL, a driver language developed at the University of South Florida. The author also describes a solution to interface design that is based on a special interface data structure that supports several styles of vector generators and interactive circuit debugging.