A logic minimizer for VLSI PLA design
DAC '82 Proceedings of the 19th Design Automation Conference
Switch-Level Model and Simulator for MOS Digital Systems
Switch-Level Model and Simulator for MOS Digital Systems
Scheduling high-level blocks for functional simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An extensible object-oriented mixed-mod functional simulation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Dynamic Functional Testing for VLSI Circuits
IEEE Design & Test
Performance verification of circuits
DAC '84 Proceedings of the 21st Design Automation Conference
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This paper introduces Intel's functional CAD design environment and methodology. The generation of an accurate behavioral model for use in systems design validation and for comparisons with lower-level components is described. The need for both an RTL and a schematics simulator in Intel's hierarchical design methodology is explained. Finally, the paper shows how these two simulators have been linked together in two ways for two different purposes: for RTL-schematics verification, and for very large logic simulation runs.