A structural representation for VLSI design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new algorithm for third generation circuit simulators: the one-step relaxation method
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A hardware engine for analogue mode simulation of MOS digital circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Zeus: A hardware description language for VLSI
DAC '83 Proceedings of the 20th Design Automation Conference
An improved switch-level simulator for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
The second generation motis mixed-mode simulator
DAC '84 Proceedings of the 21st Design Automation Conference
Functional design verification by multi-level simulation
DAC '84 Proceedings of the 21st Design Automation Conference
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The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open", "closed", or "indeterminate". Many characteristics of 140S circuits can be modeled accurately, including: ratioed, complementary, and precharged logic-, dynamic and static storage; (bidirectional) pass transistors; busses; charge sharing; and sneak pa ths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and has been used to simulate circuits containing over 10,000 transistors. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.