A data structure for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Switch-Level Model and Simulator for MOS Digital Systems
Switch-Level Model and Simulator for MOS Digital Systems
Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
IEEE Transactions on Computers
Algorithms for accuracy enhancement in a hardware logic simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing verification by formal signal interaction modeling in a multi-level timing simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient simulation of bipolar digital ICs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental event-driven simulation of digital FET circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Model development and verification for high level analog blocks
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Simulation of coupling capacitances using matrix partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A new algorithm for third generation circuit simulators: the one-step relaxation method
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A transistor-level logic-with-timing simulator for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Design Verification of the WE 32106 Math Accelerator Unit
IEEE Design & Test
Post-Layout Verification of the WE DSP32 Digital Signal Processor
IEEE Design & Test
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
Simulation based verification of register-transfer level behavioral synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper describes the second generation MOTIS mixed-mode simulator. In particular, it extends the current modeling capabilities to include resistors, floating capacitors, and bidirectional transmission gates. It employs a relaxation algorithm with local time-step control for timing simulation, and a switch level approach for unit delay simulation. It provides logic and timing verification for general MOS circuits in a mixed-mode environment. The new simulator is being used for production chips, and it is more accurate, flexible, and efficient than the existing MOTIS mixed-mode simulator.