Exclusive simulation of activity in digital networks
Communications of the ACM
Multi-sim, a dynamic multi-level simulator
DAC '78 Proceedings of the 15th Design Automation Conference
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
Operational features of an MOS timing simulator
DAC '75 Proceedings of the 12th Design Automation Conference
SABLE: A tool for generating structured, multi-level simulations
DAC '79 Proceedings of the 16th Design Automation Conference
Hierarchical modeling and simulation in VISTA
DAC '79 Proceedings of the 16th Design Automation Conference
An object-oriented swicth-level simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A multiple media delay simulator for MOS LSI circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Design aids for the simulation of bipolar gate arrays
DAC '83 Proceedings of the 20th Design Automation Conference
A data structure for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
The second generation motis mixed-mode simulator
DAC '84 Proceedings of the 21st Design Automation Conference
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
Survey of analysis, simulation and modeling for large scale logic circuits
DAC '81 Proceedings of the 18th Design Automation Conference
Process oriented logic simulation
DAC '81 Proceedings of the 18th Design Automation Conference
A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge
DAC '81 Proceedings of the 18th Design Automation Conference
Designer's Workbench: Delivery of cad tools
DAC '82 Proceedings of the 19th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
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To provide flexibility and efficiency in logic and timing verification of MOS VLSI circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. Such a capability is provided by the Mixed-Mode Simulator described here. This simulator allows different elements of a circuit to be modeled and simulated at different levels of detail. The modeling levels are MOS transistor level, logic gate level and functional level. The simulation levels are timing, multiple delay and unit delay. The simulator is being used on production LSI chips and its performance is discussed.