Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Chip layout optimization using critical path weighting
25 years of DAC Papers on Twenty-five years of electronic design automation
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Comparison of CMOS PLA and polycell representations of control logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Designing Circuits with Partial Scan
IEEE Design & Test
An Expert System to Automate Timing Design
IEEE Design & Test
Post-Layout Verification of the WE DSP32 Digital Signal Processor
IEEE Design & Test
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
DAC '83 Proceedings of the 20th Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Software optimization for MPSoC: a mpeg-2 decoder case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
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For verifying the timing performance of synchronous MOS circuits a path analysis facility has been developed in the MOTIS (MOS Timing Simulator) system. This path analysis traces the clock signals to the latches in the circuit, computes the clock skews and then performs a path search analysis between all latches. For the paths between clocked latches, the timing constraints are determined using the clock skews and the operating frequency. The paths that do not satisfy these constraints are identified as problem paths. Such an analysis does not require a prior generation of circuit stimuli that are necessary for simulation. In terms of complexity also, it is simpler than simulation.