Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Testable path delay fault cover for sequential circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting multicycle false paths in the performance optimization of sequential logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper outlines several problems relatedto the delay fault testing of sequential circuits. For timingtest of a circuit and for layout optimization, critical pathdata are needed. When critical paths are identified by astatic timing analyzer, many of the selected paths cannotbe activated functionally. Such paths are sequential falsepaths. However, many of these paths can be activatedand tested in the full or partial scan mode due to theincreased controllability and observability. Therefore, itis possible that detection of a timing error on a sequentialfalse path, when scan mode is used, can lead to the rejectionof a functionally good circuit. We propose that thesepaths should not be targeted during delay test if scanmode is used. Similarly, sequential false paths should notbe used for layout optimization or for selection of maximumclock rate. We present a novel algorithm to identifythese paths. This algorithm is based on functional analysisof each target path for single and multiple path activation.If a path cannot be activated either way, it is sequentiallyfalse.