Testable path delay fault cover for sequential circuits

  • Authors:
  • A. Krstić;K. Cheng;S. Chakradhar

  • Affiliations:
  • Department of ECE, University of California, Santa Barbara, CA;Department of ECE, University of California, Santa Barbara, CA;C&C Research Laboratories, NEC, Princeton, NJ

  • Venue:
  • EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
  • Year:
  • 1996

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Abstract