The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simulation-Based Engineering for Industrial Competitive Advantage
IEEE Design & Test
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy models for delay testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Functionally Testable Path Delay Faults on a Microprocessor
IEEE Design & Test
A Novel Solution for Chip-Level Functional Timing Verification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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