Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Testable path delay fault cover for sequential circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An implication-based method to detect multi-cycle paths in large sequential circuits
Proceedings of the 39th annual Design Automation Conference
Enhancing the performance of multi-cycle path analysis in an industrial setting
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
Proceedings of the 17th ACM Great Lakes symposium on VLSI
On-line functionally untestable fault identification in embedded processor cores
Proceedings of the Conference on Design, Automation and Test in Europe
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We address the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions. This is because no instruction sequence can produce a test sequence which can sensitize the path and capture the fault effect into the destination output/flip-flop at-speed. These paths are called functionally untestable paths. We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX ) indicate that a significant percentage of structurally testable paths are functionally untestable.