Functionally Testable Path Delay Faults on a Microprocessor
IEEE Design & Test
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Untestable Fault Identification in Sequential Circuits Using Model-Checking
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement
IEEE Transactions on Dependable and Secure Computing
MTV '08 Proceedings of the 2008 Ninth International Workshop on Microprocessor Test and Verification
Microprocessor Software-Based Self-Testing
IEEE Design & Test
New techniques for untestable fault identification in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Functional testing of embedded processors is a challenging task and additional constraints are imposed when a functional test procedure has to be executed online. In the latter case, a significant amount of the processor faults cannot be detected since related to the debug/test circuitry or because of memory configuration constraints. In this paper we identify several sources of on-line functional untestability and propose a set of techniques to exactly measure their impact on the fault coverage. Experimental results related to an industrial case study are reported, showing that the fault coverage loss due to the considered untestability sources may reach more than 13%.