Automatic Generation of Instructions to Robustly Test Delay Defects in Processors

Authors:
Sankar Gurumurthy;Ramtilak Vemu;Jacob A. Abraham;Daniel G. Saab
Affiliations:
The University of Texas at Austin, USA;The University of Texas at Austin, USA;The University of Texas at Austin, USA;Case Western Reserve University
Venue:
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Year:
2007

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Abstract

We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These instruction sequences can be loaded into the cache to test the processor functionally.