On efficient generation of instruction sequences to test for delay defects in a processor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-line functionally untestable fault identification in embedded processor cores
Proceedings of the Conference on Design, Automation and Test in Europe
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These instruction sequences can be loaded into the cache to test the processor functionally.