On efficient generation of instruction sequences to test for delay defects in a processor

Authors:
Sankar Gurumurthy;Ramtilak Vemu;Jacob A. Abraham;Suriyaprakash Natarajan
Affiliations:
University of Texas, Austin, TX, USA;University of Texas, Austin, TX, USA;University of Texas, Austin, TX, USA;Intel Corporation, Santa Clara, CA, USA
Venue:
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Year:
2008

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Abstract

We present a technique that deals with the problem of efficiently generating instruction sequences to test for delay defects in a processor. These instruction sequences are loaded into the cache of a processor and the processor is run in its normal functional (native) mode to test itself. The methodology that we present avoids the significant increase in search space of a previous method while generating tests. We also present a technique which increases the probability of detecting multiple delay faults with a single instruction sequence. This technique can help immensely in reducing the cost of test. We demonstrate the effectiveness of our technique on an off-the shelf processor.