Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Software-based diagnosis for processors
Proceedings of the 39th annual Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay defect screening for a 2.16GHz SPARC64 microprocessor
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Improving Transition Delay Test Using a Hybrid Method
IEEE Design & Test
Simulation-Based Functional Test Generation for Embedded Processors
IEEE Transactions on Computers
A delay fault model for at-speed fault simulation and test generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
On efficient generation of instruction sequences to test for delay defects in a processor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions. This is because no instruction sequence can produce a test sequence, which can sensitize the path and capture the fault effect into the destination out put/flip-flop at-speed. These paths are called functionally untestable paths.We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance and illustrate that they do not need to be tested if the delay defect does not cause the path delay to exceed twice the clock period. Under the assumption that delay defects causing the path delay to exceed twice the clock period will be detected by tests for transition faults, the identified functionally untestable paths do not need to be targeted for path delay testing.We describe a method to identify functionally untestable paths. The main components of our method are: (1) using the microprocessor's RTL description, we extract the spatial and temporal correlations among registers and flip-flops in the microprocessor and (2) we use the extracted constraints to identify functionally untestable paths. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable and thus need not be tested.