Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
Journal of Electronic Testing: Theory and Applications
Maximizing Impossibilities for Untestable Fault Identification
Proceedings of the conference on Design, automation and test in Europe
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Efficient Multiphase Test Set Embedding for Scan-based Testing
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Scan-based transition tests are added to improve the detection of speed failures in sequential circuits. Empirical data suggests that both data volume and application time will increase dramatically for such transition testing. Techniques to address the above problem for a class of transition tests, called enhanced transition tests, are proposed in this article.The first technique, which combines the proposed transition test chains with the ATE repeat capability, reduces test data volume by 46.5&percent; when compared with transition tests computed by a commercial transition test ATPG tool. However, the test application time may sometimes increase. To address the test time issue, a new DFT technique, Exchange Scan, is proposed. Exchange scan reduces both data volume and application time by 46.5&percent;. These techniques rely on the use of hold-scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues. In addition, we address the problem of yield loss due to incidental overtesting of functionally-untestable transition faults, and we formulate an efficient adjustment to the algorithm to keep the overtest ratio low. Our experimental results show that up to 14.5&percent; reduction in overtest ratio can be achieved, with an average overtest reduction of 4.68&percent;.