Using a single input to support multiple scan chains

Generating efficient tests for continuous scan

Proceedings of the 38th annual Design Automation Conference

Extending OPMISR beyond 10x Scan Test Efficiency

IEEE Design & Test

A cost-effective scan architecture for scan testing with non-scan test power and test application cost

Proceedings of the 40th annual Design Automation Conference

A Case Study on t e Implementation of t e Illinois Scan Architecture

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Using MUXs Network to Hide Bunches of Scan Chains

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Efficient techniques for transition testing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

XPAND: An Efficient Test Stimulus Compression Technique

IEEE Transactions on Computers

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Concurrent core test for SOC using shared test set and scan chain disable

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Survey of Test Vector Compression Techniques

IEEE Design & Test

Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction

IEEE Transactions on Computers

Test cost reduction for SoC using a combined approach to test data compression and test scheduling

Proceedings of the conference on Design, automation and test in Europe

A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

IEICE - Transactions on Information and Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment

Proceedings of the 2009 International Conference on Computer-Aided Design

Scan cell positioning for boosting the compression of fan-out networks

Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

Scalable adaptive scan (SAS)

Proceedings of the Conference on Design, Automation and Test in Europe

A low overhead high test compression technique using pattern clustering with n-detection test support

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Capture-power-aware test data compression using selective encoding

Integration, the VLSI Journal

Computing two-pattern test cubes for transition path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems