Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Time Domain Multiplexed TAM: Implementation and Comparison
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Survey of Test Vector Compression Techniques
IEEE Design & Test
Minimizing the Impact of Scan Compression
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Hierarchical Test Compression for SoC Designs
IEEE Design & Test
Evaluation of Entropy Driven Compression Bounds on Industrial Designs
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan compression has emerged as the most successful solution to solve the problem of rising manufacturing test cost. Compression technology is not hierarchical in nature. Hierarchical implementations need test access mechanisms that keep the isolation between the different tests applied through the different compressors and decompressors. In this paper we discuss a test access mechanism for Adaptive Scan that addresses the problem of reducing test data and test application time in a hierarchical and low pin count environment. An active test access mechanism is used that becomes part of the compression schemes and unifies the test data for multiple CODEC implementations. Thus, allowing for hierarchical DFT implementations with flat ATPG.