A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design

Authors:
Vikram Iyengar;Anshuman Chandra
Affiliations:
-;-
Venue:
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2003

Citing 0
Cited 2

Test response reuse-based SoC core test compression and test scheduling for test application time minimization

Microelectronics Journal
Scalable adaptive scan (SAS)

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time boththese approaches into a single test methodology. We show how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on test data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.